This invention relates to sample resolution circuits, and more particularly to a fast digital sample resolution circuit for determining the logic level of an input signal.
In many instances in digital electronics, it is necessary to determine the logic level of a signal at a particular moment in time. For example, in interfacing asynchronous digital data signals from one circuit or source to another circuit, it is particularly necessary to synchronize the internal clock of the receiving circuit to the transmission rate of the incoming signal. One known method for such synchronization is to trigger an internal clock generator subcircuit in the receiving circuit upon receipt of a specified logic signal from the asynchronous circuit. Such a method has previously been used, for example, in synchronizing a disc controller circuit to the position of a rotating magnetic disc storage device.
In such a system, the system clock used in the controller circuit is derived by dividing a servoclock signal issued by the disc device. The system clock in the controller circuit thereby is frequency related to the rotation of the disc. Positional information is provided from the disc by a sector pulse signal. The sector pulse signal divides the disc into arcs of a given angle, each of which is reserved for a specifically addressed field of data. The phase of the system clock in the controller circuit is synchronized to the disc position by holding the servoclock divider to a pre-set condition until a sector pulse occurs during a clock pulse from the servoclock. Detection of the occurrence of the sector pulse enables the servoclock divider to begin generating the system clock, thereby providing a known phase relationship between the controller system clock and the position of the rotating disc.
One problem that occurs with this sampling and enabling technique is the difficulty of detecting that a logic state change has occurred in a sector pulse signal. There is some probability when a sector pulse signal line is sampled during a clock pulse from the servoclock that the incoming sector pulse may be in a transition from one logic state to the other. Thus, the sampling circuit may not resolve a particular sample in the required time in order to determine that the incoming sector pulse is the enabling signal for the servoclock divider circuit. If the sampling circuit does not resolve the logic value of the sector pulse properly, an anomolous logic "halfstate" may be propagated throughout a portion of the digital circuitry, causing incorrect operation.
The probability of the above situation occurring is proportional to the amount of time the incoming sector pulse is in transition relative to the rate of the servoclock period, and to the ability of the sampling circuit to resolve any sample value to an acceptable logic level (logic 0 or logic 1) during the servoclock time period.
As the incoming clock rate increases, it becomes increasingly important to resolve any sample value to an acceptable logic level in a correspondingly shorter period of time, and faster sampling circuits are required since prior art methods of sampling and resolving input data values are not adequate.
It is therefore an object of this invention to provide a new and improved fast digital sample resolution circuit that rapidly resolves the logic state of an input signal. The present invention achieves the above function with a simple and inexpensive metal oxide semiconductor (MOS) field effect transistor (FET) circuit, described in full below.